Quantum AI Report

The convergence of Quantum with AI

Superconducting

Qubits built from superconducting circuits cooled to near absolute zero. The most industrially mature approach, favoured by IBM, Google, and Rigetti; fast gates, but short coherence times and demanding cryogenics.

61 stories

arXiv quant-ph

Data and code for collision-model Dicke-state preparation: depth-fidelity frontiers, circuit costs, and superconducting-processor measurements

Researchers released the data and code accompanying a study of collision-model preparation of Dicke states. The work reports depth–fidelity trade-offs, circuit resource costs, and measurements taken on superconducting quantum processors. Dicke states are multipartite entangled states with a fixed number of excitations shared across qubits, relevant to quantum sensing and networking.

OutlookPlausible

The released code and measured baselines could let other groups test whether collision-model Dicke-state circuits reduce depth enough to become a standard preparation route for fixed-excitation sensing states on noisy superconducting processors.

arXiv quant-ph

Bunny Codes: Broadening Superconducting Quantum Error Correction Capability through Advanced Control Engineering

A preprint studies superconducting quantum error correction for qLDPC codes with nonlocal stabilizers. It examines how an enriched native two-qubit gate set — CNOT plus CXSWAP — can simplify syndrome extraction circuits. The work, titled 'Bunny Codes,' presents an exhaustive analysis of these gate-set advantages.

OutlookPlausible

Superconducting hardware teams could adopt CXSWAP as a native gate within two years, enabling small qLDPC codes with nonlocal stabilizers to be tested on existing fixed-connectivity processors without costly SWAP decompositions.

arXiv quant-ph

Hardware-Efficient Error Mitigation and Shot-Efficient Sampling on IBM Quantum Hardware

Researchers experimentally evaluated a combination of error mitigation and finite-shot sampling techniques on an IBM Quantum superconducting processor under a constrained execution budget. The methods included calibration-aware qubit selection, circuit-depth scaling, zero-noise extrapolation, dynamical decoupling, readout-error mitigation, and repeated-shot estimation. The work focuses on hardware-efficient error mitigation and shot-efficient sampling rather than full error correction.

OutlookLikely

If the combined calibration-aware qubit selection and layered error mitigation generalizes beyond the studied circuits, this could become a default execution mode in Qiskit Runtime within two years, reducing the shot and depth cost of running noise-sensitive algorithms on IBM Quantum processors.

arXiv quant-ph

Kerr nonlinearity and three-wave mixing in superconducting resonators hosting Al-InAs weak links

Researchers report superconducting microwave resonators that incorporate aluminium-indium arsenide (Al-InAs) weak links and exhibit both cubic nonlinearity for three-wave mixing and quartic Kerr nonlinearity. The work examines these nonlinearities in the context of parametric amplification and continuous-variable quantum information tasks, noting that quartic contributions can limit device performance.

OutlookPlausible

Within two years, these Al-InAs weak-link resonators could be engineered to suppress the quartic Kerr term enough to serve as on-chip three-wave mixing elements for Josephson parametric amplifiers or continuous-variable entanglement sources.

The Quantum Insider

Researchers Use IBM Quantum Computer to Test Drug-Docking Method

A research team used IBM quantum hardware to test a drug-docking method, as reported by The Quantum Insider. The work focuses on molecular docking calculations used in drug discovery. The available abstract does not include specific performance or accuracy results.

OutlookPlausible

Pharmaceutical research groups could begin benchmarking this quantum drug-docking method against classical docking tools on IBM's cloud-accessible superconducting processors within two years.

arXiv quant-ph

Reinforcement Learning for Robust Calibration of Multi-Qudit Quantum Gates

A preprint on arXiv proposes a hybrid optimization framework for calibrating gates in qudit-based quantum processors. The approach couples optimal control theory with reinforcement learning, specifically a contextual decision-making component, to address spectral crowding and limited controllability in higher-dimensional systems. The abstract describes the method's design but does not include experimental benchmarks.

OutlookPlausible

Within two years, the hybrid framework could be implemented on ion-trap or superconducting qudit testbeds to improve single- and two-qudit gate fidelities without exhaustive gate set tomography.

arXiv quant-ph

High-Fidelity Entangled States in a Connectivity-Four Fluxonium Quantum Processor

Researchers have built a fluxonium quantum processor using lumped-element resonator couplers and report the first connectivity-four unit cell for this qubit type. The device produces high-fidelity entangled states across the four-qubit cell. The work addresses the challenge of moving fluxonium qubits from linear chains to two-dimensional lattices suitable for quantum error correction.

OutlookPlausible

Within two years, this coupler approach could be used to assemble a small fluxonium surface-code patch and benchmark logical error rates against transmon-based devices.

arXiv quant-ph

Low-leakage superconducting-qubit measurement with sub-100-ns total duration

Researchers demonstrated a superconducting transmon measurement with a total duration of 97(1) ns, timed from the start of the measurement pulse until the measurement-induced error on a subsequent π-pulse operation dropped below the specified threshold. The work is framed as progress on fast, accurate, low-leakage readout for quantum error correction.

OutlookPlausible

This could shorten syndrome extraction cycles in superconducting surface-code prototypes, cutting idle error accumulation during error-correction rounds.

IBM Completes Acquisition of HRL Laboratories to Expand Multi-Modality Quantum Roadmap

IBM has completed its acquisition of HRL Laboratories, a Malibu-based R&D institution. The deal brings HRL's silicon-spin qubit, quantum sensing, cryogenics, and advanced materials expertise under IBM's quantum umbrella. IBM says this complements its existing superconducting qubit work and supports a dual-track hardware roadmap.

OutlookPlausible

IBM could bring silicon-spin qubit test chips into its existing cryogenic and control stack within two years, giving it a second hardware modality alongside superconducting processors.

HPCwire

IBM Completes HRL Laboratories Acquisition to Advance Quantum Hardware Roadmap

IBM completed its acquisition of HRL Laboratories, an R&D institution with expertise in quantum computing, quantum sensing, materials science, and advanced technologies. IBM states the combination will bring complementary capabilities to bear on its quantum hardware roadmap.

OutlookPlausible

IBM could incorporate HRL's silicon fabrication and cryogenic control techniques into its superconducting quantum processors, improving qubit coherence and reducing control wiring overhead in upcoming large-scale systems.

arXiv quant-ph

To Scale Up or To Scale Out: Evaluating Space-Time Costs of Compiled Logical Circuits on Modular Superconducting Quantum Processors

A new arXiv preprint evaluates space-time costs of compiled logical circuits on modular superconducting quantum processors, comparing scale-up (larger monolithic chips) against scale-out (multiple chips with interconnects). The authors compile fault-tolerant circuits and assess overheads from routing and inter-module links. The study provides cost models intended to guide architecture choices for error-corrected superconducting systems.

OutlookPlausible

This analysis could help superconducting hardware teams decide between monolithic scale-up and modular scale-out for near-term fault-tolerant demonstrations, potentially focusing investment on the cheaper dimension and accelerating early logical qubit prototypes.

Quantum X Labs Outperforms PyMatching Benchmarks on Google Quantum Hardware Surface-Code Dataset Using NVIDIA CUDA-Q

Quantum X Labs reported that its surface-code decoder outperformed PyMatching on a dataset derived from Google quantum hardware. The benchmark used NVIDIA CUDA-Q for acceleration.

OutlookPlausible

This could enable real-time decoding for superconducting surface-code processors within two years if the CUDA-Q decoder maintains low latency on live hardware.

Quantum Zeitgeist

Quantum X Labs decoder beats benchmarks on Google’s dataset

Quantum X Labs reported that its quantum error correction decoder outperformed existing benchmark decoders on a dataset made public by Google. The dataset is associated with Google's superconducting qubit error correction experiments, though specific performance metrics were not detailed in the announcement.

OutlookPlausible

If the decoder's speed advantage holds in realistic settings, it could be integrated into existing superconducting quantum stacks within two years, reducing logical error rates on current devices without requiring hardware changes.

The Quantum Insider

Quantum X Labs Tests AI Quantum Error Decoder on Google Hardware Dataset

Quantum X Labs tested an AI quantum error decoder on a dataset from Google quantum hardware. The evaluation applied the decoder to real device noise rather than simulated error models. No detailed performance metrics or logical error rate benchmarks were disclosed in the announcement.

OutlookPlausible

If the decoder demonstrates improved accuracy on Google's hardware noise profile, it could become a candidate for integration into superconducting error-correction stacks within two years, reducing decoding latency for near-term fault-tolerance experiments.

arXiv quant-ph

Simulating Black Hole Thermality and Interior Scrambling on a Superconducting Quantum Processor

An arXiv preprint reports simulating black hole thermality and interior scrambling on a superconducting quantum processor. The work maps black hole physics onto qubit dynamics, probing information scrambling through measurements accessible to near-term hardware.

OutlookPlausible

This could enable superconducting quantum processors to become testbeds for probing black hole information scrambling beyond classical simulability.

IBM Links Modular Cryogenic Cells to Scale Multi-Chip Architectures for 2029 Starling Quantum Computer

IBM has linked modular cryogenic cells, a step toward scaling multi-chip superconducting quantum processors for its 2029 Starling quantum computer. The milestone demonstrates a path to connect multiple refrigeration units, allowing larger qubit counts than a single cryostat can support.

OutlookPlausible

Within two years, IBM could use linked cryogenic cells to prototype multi-chip logical qubit experiments spanning separate refrigeration units, testing distributed fault-tolerance before the full Starling system is built.

HPCwire

IBM Links Cryogenic Modules to Advance Fault-Tolerant Quantum Computing

IBM reported linking cryogenic modules to enable communication between quantum processors operating at low temperatures. The demonstration is positioned as a step toward building larger, fault-tolerant superconducting quantum systems.

OutlookPlausible

IBM could begin combining multiple cryogenic modules into a single logical quantum processor, bypassing the physical qubit limits of one dilution refrigerator.

The Quantum Insider

IBM Connects Two Modular Cryogenic Systems for Quantum Computing

IBM has connected two modular cryogenic systems for quantum computing, according to reporting by The Quantum Insider. The development was published on 19 August 2026. The systems are part of IBM's superconducting quantum hardware effort.

OutlookPlausible

Within two years, this could allow IBM to link multiple smaller cryostats into a single logical quantum processor, sidestepping the engineering limits of one large dilution refrigerator.

arXiv quant-ph

Fault-Tolerant Non-Clifford GKP Gates using Polynomial Phase Gates and On-Demand Noise Biasing

An arXiv preprint proposes a fault-tolerant scheme for non-Clifford gates on GKP-encoded qubits, combining polynomial phase gates with on-demand noise biasing. The approach targets universal fault-tolerant quantum computing by reducing the overhead of non-Clifford operations in bosonic error-corrected architectures.

OutlookPlausible

This could enable near-term demonstrations of low-overhead fault-tolerant non-Clifford gates in superconducting cavity QED systems, where GKP qubits are already being developed.

arXiv quant-ph

Spectator Leakage Suppression via Invariant Subspace Engineering for CZ Gates in Superconducting Quantum Circuits

An arXiv preprint proposes an invariant subspace engineering method to suppress spectator leakage during controlled-Z gates in superconducting quantum circuits. The approach targets unwanted transitions in non-target qubits during two-qubit operations. The authors report suppression of leakage to higher excited states in spectator qubits.

OutlookPlausible

This could enable fixed-frequency transmon architectures to achieve higher two-qubit gate fidelities by reducing a dominant coherent error source, potentially improving near-term error correction experiments.