IQM Quantum Computers will deploy LUMI-IQ, a superconducting quantum computer designed to support logical qubits, at CSC's Kajaani, Finland data center. The EuroHPC Joint Undertaking is co-funding the system, which will be integrated into the LUMI AI Factory as a hybrid HPC-AI-quantum platform. Delivery is planned in three phases through 2029, beginning with 150 physical qubits.
OutlookPlausible
European researchers could begin co-scheduling quantum and classical HPC jobs within the existing LUMI environment in the next two years, testing hybrid algorithms before the full logical-qubit system is complete.
Researchers at Chalmers University of Technology have reported a method using quantum lattice gates to perform bosonic quantum operations in a single Floquet driving period, replacing many repeated cycles. The technique accelerates these operations by up to 1,000 times and is aimed at making bosonic quantum error correction faster and more robust.
OutlookPlausible
Within two years, this could let superconducting bosonic qubits run enough error-correction cycles per coherence time to demonstrate improved logical qubit lifetimes on small codes.
A preprint on arXiv proposes using dual-unitary circuits in a brickwork arrangement as the reservoir layer for quantum reservoir computing. The authors argue the architecture is compatible with noisy intermediate-scale quantum devices, and they explore its use for encoding and processing information.
OutlookPlausible
Dual-unitary QRC could become a standard numerical and experimental benchmark for quantum reservoir computing within two years.
Qedma Quantum Computing and the HQC² research consortium applied their QESEM software error-mitigation layer to IBM's Aachen superconducting quantum processor. The method reduced energy estimation errors for a water molecule's potential energy surface in quantum chemistry calculations by 30–50 times. The demonstration began from an error of roughly 500 mHa.
OutlookPlausible
If the error reduction generalizes beyond the water benchmark, QESEM could be integrated into existing cloud-based quantum chemistry workflows on superconducting hardware, making small-molecule energy estimates accurate enough to support hybrid classical-quantum calculations within two years.
Rigetti Computing announced that its wholly owned subsidiary, Rigetti & Co, LLC, has signed a definitive agreement with the U.S. Department of Commerce for $100 million in CHIPS Research and Development funding. The award is intended to accelerate Rigetti's superconducting quantum computing R&D.
OutlookPlausible
The funding could accelerate Rigetti's move from single-chip superconducting processors to modular multi-chip systems within the next two years.
Rigetti has been awarded $100 million by the U.S. government. The funding is intended for research and development in superconducting quantum computing. The work will target key challenges in scaling these systems.
OutlookPlausible
The award could let Rigetti prototype a larger modular multi-chip superconducting processor within two years by funding work on packaging, wiring, and control bottlenecks that currently limit qubit counts.
D-Wave has been awarded up to $100 million through the U.S. CHIPS Act to expand its quantum computing hardware efforts. The funding supports its dual-platform strategy, covering both quantum annealing and gate-model systems.
OutlookPlausible
D-Wave could use the federal funding to bring a gate-model processor to its Leap cloud service within two years, giving existing annealing customers an on-ramp to circuit-model workloads.
NEC Corporation has ended its research and development of superconducting quantum computers. The company will shift toward quantum-inspired annealing and classical emulation, concentrating on software and optimization services. Fujitsu remains the main Japanese corporate developer of superconducting quantum hardware.
OutlookPlausible
NEC could package its annealing and classical emulation capabilities into commercial optimization services for Japanese enterprises within the next two years.
A preprint on arXiv reports a study applying quantum graph neural networks to jet classification, motivated by jet measurements at the Large Hadron Collider and the future Electron-Ion Collider. The authors explore quantum machine learning methods for jet tagging and present an implementation intended to run on quantum hardware.
OutlookPlausible
This preprint could become a reference benchmark for quantum GNN jet tagging on small datasets, with follow-up papers testing variations in encoding and circuit depth across cloud-accessible quantum processors.
A new preprint describes TETRIS-Q, a tiling-based technique intended to reduce transient faults in superconducting qubits caused by external radiation. It positions radiation-induced errors as a remaining challenge even amid progress in quantum error correction. The abstract introduces the method but does not report experimental validation in the available excerpt.
OutlookSpeculative
If the tiling scheme can be applied to existing interleaved superconducting qubit layouts, it could within two years be integrated into quantum error correction experiments to reduce radiation-induced correlated errors without new hardware.
A new benchmarking study tests whether surface-code decoder rankings derived from simulated noise models hold on real quantum hardware. It uses Google's Willow processor, a device that has operated below the surface-code error-correction threshold, as the hardware testbed.
OutlookPlausible
If decoder rankings transfer from simulation to Willow-class hardware, error-correction teams could select and optimise surface-code decoders largely in simulation, reducing the need for repeated on-device benchmarking during early logical qubit experiments.
NEC has decided to halt development of quantum computer hardware, according to The Quantum Insider. The move shifts NEC away from building its own quantum computer systems.
OutlookPlausible
NEC could pivot to quantum software, integration, and managed services, using third-party quantum hardware to serve its existing enterprise customers.
IBM has made its Nighthawk r2 processor available on the IBM Quantum Platform. The 120-qubit device introduces a qubit-reset architecture that IBM reports delivers up to 25 times the circuit throughput of its Heron systems, exceeding 100,000 circuits per second.
OutlookPlausible
This throughput increase could make practical quantum error mitigation techniques that require large numbers of circuit executions, improving the quality of results on Nighthawk r2 for chemistry and optimization workloads within the next two years.
IBM Quantum announced a new superconducting processor, Nighthawk r2, with 120 programmable qubits. The company reports that it executes circuits 25 times faster than its previous Heron-generation processors. The processor is positioned for quantum error correction work.
OutlookPlausible
The faster circuit execution could allow IBM to run deeper, more frequent error-correction cycles within the next two years, making it feasible to demonstrate repeated stabilizer measurements and logical qubit performance on Nighthawk r2.
George Mason University has entered a strategic hardware partnership with Oxford-based quantum infrastructure firm TreQ to deploy an open-architecture quantum computer at its Northern Virginia campus. The $7.7 million system is backed by catalytic funding from the Virginia Innovation Partnership Corporation and university capital.
OutlookPlausible
GMU's open-architecture QPU could become a regional testbed where Virginia-based defense and technology firms evaluate modular quantum hardware without owning their own systems, shortening integration cycles for hybrid classical-quantum workloads.
superconductingGeorge Mason UniversityTreQVirginia Innovation Partnership Corporation Rigetti Computing and Purdue University have published joint research extending Rigetti's quantum preconditioning framework to hard-constrained combinatorial optimization problems. The method uses two-point variable correlations extracted from shallow QAOA circuits to modify the problem's objective function before it is passed to a classical solver.
OutlookPlausible
Within two years, this framework could become a standard preprocessing step in Rigetti's cloud service, letting users submit constrained optimization problems, receive QAOA-derived correlation data, and warm-start commercial classical solvers.
Qilimanjaro reported a machine learning readout with 99.9% accuracy in quantum reservoir computing experiments. The approach trains only the readout layer, leaving the quantum reservoir itself untrained, and is positioned as a response to rising classical ML training costs.
OutlookPlausible
If 99.9% readout accuracy holds outside controlled experiments, Qilimanjaro's superconducting reservoir hardware could become a practical near-term platform for low-overhead time-series forecasting, such as energy demand or sensor prediction.
A preprint describes a microwave-free approach to preparing and measuring the state of superconducting qubits. It targets the calibrated microwave signals and roughly 100 ns measurement times that the authors identify as obstacles to scaling superconducting quantum processors.
OutlookPlausible
If the method's fidelity and speed hold up outside the lab, it could be folded into cryogenic control stacks for multi-qubit superconducting processors within two years, reducing per-qubit microwave calibration overhead.
A new arXiv preprint addresses fault-tolerant quantum computation using bosonic qubits, focusing on dual-rail and cat encodings together with bias-preserving gates. The authors frame the problem around the need for universal logical operations, suppression of hardware-specific noise, and efficient handling of photon-loss errors, noting that each encoding alone has attractive features but also important limitations.
OutlookPlausible
If the proposed dual-rail cat code construction can be implemented in existing superconducting cavity or photonic platforms, it could enable near-term experiments demonstrating bias-preserving gates and error correction that simultaneously address photon loss and hardware noise.
Researchers propose a hierarchical quantum error correction scheme that concatenates hypergraph product codes as an outer layer with rotated surface codes as an inner layer. The design is compatible with quantum processors limited to nearest-neighbor interactions. The outer code uses (3,4)-random HGP codes, which are known for their constant encoding rate.
OutlookPlausible
This hierarchical scheme could become a benchmark for fault-tolerant circuit simulations on nearest-neighbor hardware, guiding which code families to prioritize for early logical qubit demonstrations.