Researchers demonstrated that the spatial location of lost neutral atoms within a quantum error-correcting code affects logical error rates, not just the total number lost. By optimising how qubit loss is managed inside the code, they improved logical error rates in up to 73% of tested scenarios, with gains reaching 5.3× under realistic conditions.
OutlookPlausible
Neutral atom quantum processors could tolerate higher atom loss rates without sacrificing logical qubit quality, reducing the need for fast atom reloading and making error-corrected operation feasible on current hardware.
IQM Quantum Computers will deploy LUMI-IQ, a superconducting quantum computer designed to support logical qubits, at CSC's Kajaani, Finland data center. The EuroHPC Joint Undertaking is co-funding the system, which will be integrated into the LUMI AI Factory as a hybrid HPC-AI-quantum platform. Delivery is planned in three phases through 2029, beginning with 150 physical qubits.
OutlookPlausible
European researchers could begin co-scheduling quantum and classical HPC jobs within the existing LUMI environment in the next two years, testing hybrid algorithms before the full logical-qubit system is complete.
A preprint posted to arXiv quant-ph introduces a technique called lifted surgery for reducing the time overhead of logical operations in quantum low-density parity-check codes. The work focuses on code surgery, a space-efficient method for fault-tolerant logical measurements, where cost builds up through repeated measurement rounds.
OutlookSpeculative
If lifted surgery reduces the number of measurement rounds without compromising fault tolerance, it could make QLDPC-based logical processors more practical for near-term demonstrations by lowering runtime overhead.
Researchers have proposed a fault-tolerant quantum computer design that operates in two spatial dimensions using only geometrically local operations. The construction combines topological codes with local classical processing and bounded-speed communication, avoiding the need for higher-dimensional connectivity or non-local decoders. It maintains a constant qubit density.
OutlookPlausible
This could enable near-term demonstrations of fault-tolerant operation on 2D superconducting or silicon spin qubit chips by replacing non-local decoder wiring with local classical logic.
An arXiv preprint reports the experimental demonstration of a logical Bell-state measurement that exceeds the linear-optical limit. The paper frames the result within fault-tolerant quantum computing, where Bell-state measurements are building blocks for measurement-based and fusion-based quantum computation and for quantum networks.
OutlookPlausible
If the logical Bell-state measurement can be integrated with existing photonic encodings, it could allow fusion-based photonic quantum processors to replace standard linear-optical fusion operations with higher-success logical variants, reducing the overhead required for fault-tolerant operation within the next two years.
A preprint on arXiv introduces two zero-overhead 'walking' circuits for Floquet codes aimed at reducing qubit leakage. The authors argue that leakage undetectably takes qubits out of the computational subspace, creating correlated errors across space and time that lower a code's threshold and effective distance. The proposed circuits are designed to address this leakage without adding overhead.
OutlookPlausible
Within two years, these walking circuits could be integrated into existing Floquet-code and surface-code demonstrations on superconducting or trapped-ion hardware to suppress leakage-induced correlated errors and extend logical qubit lifetimes.
Researchers at Chalmers University of Technology have reported a method using quantum lattice gates to perform bosonic quantum operations in a single Floquet driving period, replacing many repeated cycles. The technique accelerates these operations by up to 1,000 times and is aimed at making bosonic quantum error correction faster and more robust.
OutlookPlausible
Within two years, this could let superconducting bosonic qubits run enough error-correction cycles per coherence time to demonstrate improved logical qubit lifetimes on small codes.
Xanadu and AMD have released Backline, an open-source extension for PennyLane designed to link quantum processors to classical compute resources including CPUs, GPUs, FPGAs, and SmartNICs. The framework provides Python-native, microsecond-scale communication aimed at removing the data bottleneck between classical and quantum systems for workloads such as quantum error correction.
OutlookPlausible
Backline could make real-time quantum error correction experiments practical on near-term quantum processors by supplying microsecond-latency feedback between quantum hardware and classical decoders.
A new decoding framework combines belief propagation with the Tesseract algorithm to reduce the computational cost of decoding certain quantum low-density parity-check codes. At realistic error rates, this hybrid approach runs fifteen times faster than the prior method without a loss in accuracy. The result applies to a specific class of qLDPC codes.
OutlookPlausible
If the speedup holds for the qLDPC code families used in experimental systems, this could enable real-time decoding of larger code distances on existing classical control hardware within the next two years.
A research paper describes a learning-based framework that takes only an encoding circuit as input and constructs physical implementations of logical operations for arbitrary quantum error-correcting codes. The approach is intended to work for non-additive codes that lack a stabilizer description, where discovering such operations is otherwise difficult.
OutlookPlausible
This framework could make non-additive quantum error-correcting codes practically explorable by synthesizing logical gates that previously had no straightforward construction path.
A new arXiv preprint describes a fault-tolerant quantum computing architecture for neutral-atom arrays that treats qubit loss as a distinct error channel. The authors note that loss accumulates during operations and atom transport, and that standard error correction aimed at stochastic Pauli errors is not sufficient on this platform.
OutlookPlausible
A loss-correcting architecture could be trialled on existing neutral-atom testbeds such as those from QuEra or Pasqal within two years by adding loss-aware decoding to their current rearrangement and mid-circuit measurement capabilities.
A new arXiv preprint describes techniques to accelerate A*-based decoding for quantum low-density parity-check (QLDPC) codes. The work builds on the Tesseract decoder, which uses A* search to find the most likely error patterns but encounters very large search graphs in practice. The abstract indicates the acceleration targets these large graphs, though the provided abstract ends before detailing the method or results.
OutlookPlausible
If the proposed acceleration delivers meaningful runtime reductions, it could make optimal A*-based QLDPC decoding practical for near-term quantum error correction experiments, lowering logical error rates during fault-tolerance benchmarks.
A preprint describes a compilation approach that takes Python-defined quantum workloads and targets a mix of CPUs, GPUs, and FPGAs, with the stated goal of meeting the low-latency demands of real-time quantum error correction. It positions the gap between accessible Python tooling and production fault-tolerant execution as a key bottleneck.
OutlookPlausible
If the proposed compiler can deterministically map latency-critical decoder operations to FPGAs while using CPUs and GPUs for higher-latency tasks, it could enable live, low-latency error correction loops for small logical qubits within two years.
PsiQuantum finalized a $100 million CHIPS Act award with the U.S. Department of Commerce to accelerate domestic semiconductor process development for fault-tolerant quantum computing. The funding is directed at 300mm wafer production of barium titanate and optimization of single-photon sources.
OutlookPlausible
PsiQuantum could bring barium titanate photonic component fabrication onto 300mm wafers at a domestic facility within two years, giving it an onshore supply of single-photon sources for iterative device testing.
IonQ has published a study describing a fault-tolerant quantum computing architecture called 'Walking Cat' that uses qLDPC codes and 19,397 physical qubits. The estimate indicates the architecture could break 256-bit elliptic curve cryptography, including schemes used to secure Bitcoin, in 25.7 days. The publication highlights the future vulnerability of current cryptographic standards and urges migration to quantum-resistant alternatives.
OutlookPlausible
This resource estimate could prompt standards bodies and regulated industries to accelerate post-quantum cryptography migration timelines, treating 256-bit ECC as breakable with fewer physical qubits than previously assumed.
IonQ announced Superion 256, its sixth-generation trapped-ion quantum computing platform, manufactured with SkyWater. The company said the first ions have been trapped in the system and it is accepting orders for customer delivery beginning in 2027.
OutlookPlausible
If SkyWater's manufacturing process yields repeatable trap arrays, Superion 256 could let early customers begin on-premises error-corrected demonstrations within two years of delivery, rather than waiting for a separate fault-tolerant product line.
IonQ published a paper describing a fully compiled, end-to-end quantum resource blueprint for attacking 256-bit elliptic-curve signatures. The model estimates that a machine with 20,000 qubits could complete such a break in under 26 days. The paper frames this as a concrete warning to accelerate migration to post-quantum cryptography.
OutlookPlausible
This resource estimate could become the reference point that regulators and large enterprises cite when setting near-term deadlines for eliminating 256-bit ECC.
Researchers have described a compilation approach for estimating the ground-state energy of the two-dimensional Fermi-Hubbard model. The method is designed for early fault-tolerant quantum hardware and treats active volume as a primary architectural constraint, rather than relying only on non-Clifford gate counts. The work appears as an arXiv preprint.
OutlookPlausible
If the active-volume model corresponds to real early fault-tolerant devices, this compilation could enable small 2D Fermi-Hubbard ground-state energy estimations on existing hardware within the next two years.
A new preprint describes TETRIS-Q, a tiling-based technique intended to reduce transient faults in superconducting qubits caused by external radiation. It positions radiation-induced errors as a remaining challenge even amid progress in quantum error correction. The abstract introduces the method but does not report experimental validation in the available excerpt.
OutlookSpeculative
If the tiling scheme can be applied to existing interleaved superconducting qubit layouts, it could within two years be integrated into quantum error correction experiments to reduce radiation-induced correlated errors without new hardware.
Researchers introduced Lindblad Multiproduct Formulas, a quantum error mitigation technique that uses two-dimensional tensor networks contracted with loop-corrected belief propagation. The work indicates that evaluating the quantities needed for the error mitigation scheme with these tensor networks may be less computationally expensive than existing alternatives. The abstract does not detail the benchmark comparison or validation beyond the proposed method.
OutlookPlausible
Within two years, this could make multiproduct-formula error mitigation practical for noisy open-system simulations by lowering the classical cost of computing the required multi-time correlation functions.