Quantum AI Report

The convergence of Quantum with AI

QuantWare

QuantWare designs and fabricates superconducting quantum processors, which it sells as components to research labs, quantum-computing companies and universities rather than operating a machine of its own. Its chips use transmon qubits with flux-tunable couplers, and the company also offers a foundry service that fabricates processors from third-party QPU designs. Spun out of the QuTech research institute at TU Delft, it was among the first suppliers of off-the-shelf superconducting QPUs, a niche now shared with rivals such as Rigetti and IQM.

AI-written profile · not yet reviewed · 16 October 2026

Headquarters
Delft, Netherlands
Founded
2020
Status
Private

Coverage

FirstQFM Foundation Model Cuts Quantum Gate Times by 33% on QuantWare QPU via NVIDIA Computing

FirstQFM AB reported a 33% reduction in single-qubit gate times on QuantWare's 21-qubit Contralto-D21 superconducting processor while maintaining gate fidelity. The result used FirstQFM's quantum foundation model, integrated with Quantum Machines' OPX control hardware and QUA calibration stack. The model was developed with NVIDIA compute resources.

OutlookPlausible

If FirstQFM's model generalizes beyond the Contralto-D21, it could be embedded in Quantum Machines' QUA calibration stack to automate per-device gate-time optimization, shrinking tune-up time for new QuantWare chips.

algorithms softwarecryogenics controlsuperconductingFirstQFM ABNVIDIAQuantWareQuantum Machines

FirstQFM Model Cuts Single-Qubit Gate Times by 33% on QuantWare Processor

Researchers applied a quantum foundation model called FirstQFM to pulse-level control on a 21-qubit QuantWare superconducting quantum processor. Using existing calibration data, the model produced gate implementations that cut single-qubit gate times by roughly a third while preserving fidelity. The approach also improved Bell-state fidelity across five qubit pairs.

OutlookPlausible

Within two years, this could let quantum hardware vendors replace some manual calibration routines with pre-trained pulse-level models, reducing downtime and improving gate fidelity consistency across devices.