Verifiable quantum advantage in extremely low depth
A new preprint describes a quantum sampling problem that can be solved by shallow circuits built from one- and two-qubit gates, is thought to be hard for polynomial-time classical algorithms under lattice-based assumptions, and can be verified efficiently by a classical computer. The paper reports two implementations, including one with log-logarithmic circuit depth.
Why it matters
The result targets a long-standing obstacle in quantum advantage: earlier sampling demonstrations such as random circuit sampling require exponential classical resources to verify, making their claims hard to certify independently. By tying hardness to lattice-based assumptions and adding an efficient classical verifier, the proposal lowers both the required circuit depth and the verification barrier. Prior shallow-circuit advantage schemes often lacked either efficient verification or relied on assumptions with less established complexity-theoretic standing, so this work could make practical quantum advantage claims more credible and more testable on near-term hardware.
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What this could make possible
0–2 years
- Plausible
Gate-based quantum hardware vendors could demonstrate the sampling task within two years on existing devices with modest qubit counts.
Log-logarithmic depth requires far fewer sequential two-qubit gates than previous supremacy circuits, reducing the coherence-time burden on superconducting and trapped-ion platforms. Existing devices already have tens to hundreds of qubits and two-qubit gate fidelities near 99%, and the main near-term risk is whether the required number of qubits, circuit repetitions, and readout fidelity needed for verification is within current reach.
2–5 years
- Plausible
This verifiable scheme could become a standard benchmark for quantum advantage, displacing random circuit sampling in academic and commercial demonstrations.
Because verification is efficient, results can be checked by third parties without replicating exponential classical calculations. This directly addresses the criticism directed at earlier random circuit sampling claims, where classical verification was infeasible. If the sampling problem can be scaled with qubit count and noise while preserving efficient classical checks, it offers a repeatable and auditable benchmark.
5+ years
- Speculative
The lattice-based hardness link could influence post-quantum cryptography or complexity theory by providing a quantum task whose classical hardness rests on the same problems underlying lattice cryptography.
If the reduction is tight and uses standard lattice assumptions such as LWE or SIS, then a polynomial-time classical algorithm for the sampler would break those assumptions. That could create new oracle separations or support the idea of quantum advantage as a cryptographic primitive. However, the current object is a sampling problem rather than a decision problem, and further reductions would be needed before any cryptographic implication is realized.
What would have to be true
- The parameter regime of the sampler must require qubit counts and circuit repetitions that are feasible on near-term hardware while still being hard for classical simulation.
- Two-qubit gate error rates and readout fidelity must be low enough that the output distribution is not washed out; shallow depth helps but does not eliminate decoherence.
- The lattice-based hardness assumptions must hold for the chosen parameters, and no hidden structure or classical algorithm can exploit the specific circuit family.
- Classical verification must remain practically efficient for the same instance sizes that quantum hardware can run; if verification overhead scales poorly, the practical advantage narrows.
Who’s positioned
- Google Quantum AI — Has already demonstrated random circuit sampling and has superconducting hardware capable of shallow circuits; this gives an alternative with efficient verification and a path to cleaner claims.
- IBM — Its utility-scale superconducting processors and roadmap emphasize gate-based circuits; low-depth sampling could validate hardware performance without the need for full error correction.
- Quantinuum — Trapped-ion systems offer high-fidelity two-qubit gates and all-to-all connectivity, which are well suited to shallow-depth circuits and could allow this task to be run with lower overhead.
- IonQ — Similar trapped-ion advantages apply; an efficiently verifiable shallow circuit could be an early differentiator for high-fidelity gate-based platforms.
What could change this
- Classical algorithms could break the lattice-based hardness or find structure that simulates the sampler, invalidating the advantage claim.
- The specific circuit implementation may suffer from noise-induced degradation that makes verification impossible at useful scale.
- Efficient classical verification might only hold for parameter ranges unreachable by current quantum hardware.
- The result is not yet peer-reviewed and the abstract does not include full parameters; actual depth and qubit overhead may be larger than implied.