To Scale Up or To Scale Out: Evaluating Space-Time Costs of Compiled Logical Circuits on Modular Superconducting Quantum Processors
A new arXiv preprint evaluates space-time costs of compiled logical circuits on modular superconducting quantum processors, comparing scale-up (larger monolithic chips) against scale-out (multiple chips with interconnects). The authors compile fault-tolerant circuits and assess overheads from routing and inter-module links. The study provides cost models intended to guide architecture choices for error-corrected superconducting systems.
AI analysis — not reported by the source
What this could mean
- 0–2 yearsPlausible
This analysis could help superconducting hardware teams decide between monolithic scale-up and modular scale-out for near-term fault-tolerant demonstrations, potentially focusing investment on the cheaper dimension and accelerating early logical qubit prototypes.
Compiled logical circuit cost models offer concrete space-time overhead comparisons; if the link infidelity and fabrication yield assumptions in the paper match current hardware, vendors like IBM and Google could use these trade-offs to prioritize building larger single chips or multi-chip modules within the next two years.
This is a brief. The day’s lead story carries the full analysis.