Quantum Elements and USC Demonstrate Surface Code Scaling on IBM Heron
Quantum Elements and USC announced a Nature Communications paper reporting that the surface code can strengthen error protection on IBM Heron processors even when the chip's native qubit connectivity does not naturally match the code's standard layout. The work demonstrates scaling of surface code error correction on deployed superconducting hardware.
AI analysis — not reported by the source
What this could mean
- 0–2 yearsPlausible
If the demonstrated surface-code scaling holds at larger code distances, existing IBM Heron-class processors could host early logical qubits within two years without needing hardware redesigned around the code's native layout.
The result shows error protection improves despite connectivity mismatch, so the main remaining barriers are qubit count, physical error rates, and decoder performance on fixed-layout devices. These are named engineering preconditions already being addressed in IBM's superconducting roadmap.
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